Technological advances in integrated circuit (IC) industry have produced generations of ICs has smaller sizes and more complex circuits than the previous generation. Therefore, an IC design process is required for planning various predetermined patterns in order to form complex circuits in a small size.
In the IC design process, a circuit designer uses a computer program to develop a logical description of the various components that are to be in a new circuit. The logical description is then converted into a description of the individual circuit building blocks performing the desired circuit functions. The description of the individual circuit building blocks is further converted into a layout file that specifies a predetermined pattern of a reticle for exposing a wafer during a photolithographic process in order to form various layers of the IC.
While fabricating the reticle for exposing the wafer, litho-etching and other process variations may occur such that the actually formed pattern of the reticle does not match the predetermined pattern designed in the IC design process. Consequently, formation of the layer of the IC would be severely impacted by utilizing the reticle with the mismatched pattern. Therefore, accurate inspection and measurement of a patterned structure such as the reticle is highly required to avoid utilizing the reticle with mismatched pattern when forming layers of the IC. Accordingly, improvements in methods and systems for inspection of a patterned structure continue to be sought.